1. Field of the Invention
The present invention relates to dynamic-type semiconductor memory devices, and in particular to improvements of a dynamic-type semiconductor memory device with functions of simultaneously testing of a plurality of bits of memory cells during functional testing of memory cells included in a semiconductor memory device. More particularly, it relates to a configuration for and method of reliable functional testing of the semiconductor memory device.
2. Description of the Background Art
In recent years, with an increased capacity of a semiconductor memory device, a problem has arisen in that it requires a much longer period of time for functional testing of whether memory cells in the memory device are normally operating or not. That is, as the capacity of the semiconductor memory device has increased, the number of the memory cells included therein has also increased, and accordingly a problem has occurred that a time period required for functional testing of all the memory cells has greatly increased with the number of memory cells. In such configuration, functional testing is carried out in a conventional way of sequentially reading the stored contents of the memory cells on a bit-by-bit basis. A configuration with a much reduced time for functional testing was proposed in the article entitled "A reliable 1-M bit DRAM with a multi-bit-test mode" by Kumanoya et al. in the IEEE Journal of Solid State Circuits, Vol. SC-20 No. 5, Oct., pp. 909-912. The article proposed a method of simultaneously carrying out functional testing of a plurality of memory cells by simultaneously selecting the memory cells of a plurality of bits in a semiconductor memory device, and outputting a certain logic value to the outside of the memory device when logic values of information read out from the memory cells simultaneously selected are all the same. An operation mode for simultaneously carrying out functional testing of the plurality of memory cells is hereinafter referred to as a test mode. The above method of functional testing has now been in practical use.
FIG. 1 illustrates one example of a configuration of a conventional semiconductor memory device having such test mode. A simple configuration of 1-megabit random access memory (hereinafter referred to as 1 MDRAM) is shown in FIG. 1.
In FIG. 1, a memory cell array 10 is divided into four memory cell array blocks 10a, 10b, 10c and 10d. For 1 MDRAM, each of the memory cell array blocks 10a-10d has 256K-bit memory cells. Each of the memory cell array blocks 10a-10d, has a memory cell array arranged in a matrix of rows and columns, and word lines WL for selecting a row of memory cells and bit line pairs BL, BL each connecting a column of memory cells. The bit line BL and the complementary bit line BL are arranged in a pair, and each memory cell MC is provided at the intersection of the word line WL and one of the bit lines BL, BL in a pair. That is, the bit lines BL, BL provide a folded bit line scheme. Sense amplifiers 12a-12d for sensing and amplifying information of the selected memory cells are respectively provided in the memory cell array blocks 12a-12d. Each of the sense amplifiers 10a-10d comprises unit sense amplifiers each provided for a bit line pair BL, BL. Therefore, each of the sense amplifier 12a-12d comprises 512 unit sense amplifiers in case of the 1 MDRAM.
In order to select one word line i.e., one row of the memory cell array 10, i.e. in each of the memory cell array blocks 10a-10d, there are provided an address buffer 14 for generating internal row address signals RA0-RA9 responsive to externally supplied address signals A0-A9, and row decoders 16a-16d for receiving the internal row address signals RA0-RA8 from the address buffer 14 to select a word line in each memory cell array block. The row decoders 16a-16d decode the row address signals RA0-RA8 such that each selects a corresponding word line and transmit a word line driving signal WL applied from a word driver 18 onto the selected word line.
In order to select a bit line pair BL, BL from each of the memory cell array blocks 10a-10d, column decoders 20a-20d are provided for selecting corresponding bit line pairs in response to internal column address signals CA0-CA8 from the address buffer 14. The address buffer 14 receives row and column addresses in a time divisional manner to generate the internal row address signals RA0-RA9 and the internal column address signals CA0-CA9 in a time-divisional manner.
A nibble decoder 22 and a selecting gate 24 are provided for simultaneously or sequentially selecting out of 1-bit or 4-bits according to an operation mode out of 4-bit memory cells simultaneously selected in the memory cell array blocks 10a-10d. The selecting gate 24 comprises transfer gate transistors Tr1, Tr2 for connecting internal data lines DB, DB to data input/output lines I/O1, I/O1 of the memory cell array block 10a, transfer gate transistors Tr3, Tr4 for connecting the internal data lines DB, DB to a data input/output line pair I/O2, I/O2 of the memory cell array block 10b, transfer gate transistors Tr5, Tr6 for respectively connecting the internal data lines DB, DB to data input/output lines I/O3, I/O3 of the memory cell array block 10c, and transfer gate transistors Tr7, Tr8 for respectively connecting the data lines DB, DB to data input/output lines I/O4, I/O4 of the memory cell array block 10d.
The nibble decoder 22 receives an internal row address signal RA9 and an internal column address signal CA9 applied from the address buffer 14, so that only one set of transfer gate transistors in the selecting gate 24 is rendered conductive in a normal mode, while the sets of transfer gate transistors in the selecting gate 24 designated by the internal address signals RA9, CA9 are cyclically and sequentially rendered conductive in a nibble mode. The normal mode is an operation mode for carrying out 1-bit data input/output for one memory cycle (while a signal RAS is logical low or the "L" level) in the semiconductor memory device. The nibble mode is an operation mode for first selecting a 1-bit memory cell in response to a row address and a column address externally provided, and after writing or reading the memory cell data, toggling a CAS signal with the signal RAS remaining at the "L" level, and writing or reading the succeeding 3-bit memory cell data in sequence. Since the row and column addresses need not be set for each memory cell in the nibble mode, the writing/reading of the memory cell data can be carried out more rapidly than in the common normal mode of 1-bit unit.
Preamplifiers 26a-26d for amplifying the given data are provided between the selecting gate 24 and the memory cell array 10. The preamplifier 26a is provided corresponding to the memory cell array block 10a, and the preamplifiers 26b-26d are provided corresponding to the memory cell array blocks 10b-10d, respectively, as well.
For data writing, there are provided an input buffer 28 for receiving and waveform-shaping write-in data Din which are externally provided, and generating e.g. complementary internal write-in data Din, Din, a writing buffer 30 for generating an internal write signal W responsive to a write signal W, and a writing gate 32 responsive to the internal write signal W from the writing buffer 30 to be ON for transmitting the internal write-in data Din, Din from the input buffer 28 onto the internal data bus lines DB, DB. The writing gate 32 comprises a transfer gate transistor Tr10 for transmitting the internal write-in data Din onto the internal data line DB and a transfer gate transistor Tr9 for transmitting the complementary (inverted) internal write-in data Din onto the complementary data line DB.
For data reading, an output buffer 38 is provided for receiving via a reading gate 36 and outputting either the data on the internal data line DB, DB or the output of a logic operation circuit 34. The reading gate 36 selects either a complementary data pair of the internal data lines DB, DB or a complementary data pair indicating a logic result of the logic operation circuit 34 responsive to a control signal from a test control circuit 40 and sends it to the output buffer 38. The output buffer 38 outputs read-out data Dout corresponding to the complementary data pair received.
The logic operation circuit 34 receives the data read out via the preamplifiers 26a-26b and after carrying out a predetermined logic operation, outputs the logic result from the complementary data pair indicating the logic result thereof.
As peripheral circuitry for controlling the operation of the semiconductor memory device, there are provided a RAS buffer 42 for receiving a row address strobe signal RAS which is externally supplied to output an internal control signal RAS, a word driver 18 for generating a word line driving signal WL in response to the internal control signal from RAS buffer 42, a sense amplifier control circuit 44 for generating activating signals SO, SO to the respective sense amplifiers 12a-12d in response to the signal from the word driver 18, and a CAS buffer 46 for receiving a column address strobe signal CAS externally provided to generate an internal control signal. The internal control signal from the RAS buffer 42 defines an operation timing of a row selection circuitry in the semiconductor memory device. On the other hand, the internal control signal from the CAS buffer 46 defines the operation of a column selection circuitry in the semiconductor memory device.
For switching between the functional testing mode of the semiconductor memory device and the common data output/input mode of 1-bit unit, a test control circuit 40 is provided for generating an internal test mode instructing signal responsive to a test mode instructing signal TE externally provided. The internal test mode instructing signal from the test control circuit 40 is applied to the nibble decoder 22 and the reading gate 36. The nibble decoder 22 renders all the transfer gate transistors Tr1-Tr8 of the selecting gate 24 conductive when the internal test mode instructing signal is applied. The reading gate 36 transmits the output of the logic operation circuit 34 to the output buffer 38 in response to the internal test instructing signal from the test control circuit 40.
In the foregoing configuration, the configuration in the memory cell array comprises the folded bit lines, so that all the complementary data are transmitted in pair onto the signal lines transmitting the internal data. Therefore, the bit line BL is connected to the input/output data line I/O, while the complementary bit line BL is connected to the complementary input/output data line I/O in each of the memory cell array blocks 10a-10d. Similarly, the internal data line DB is connected to the data input/output line I/O, while the complementary internal data line DB is connected to the complementary internal data input/output line I/O. Next, the operation of this semiconductor memory device will be briefly described with reference to FIG. 1. First of all, an operation mode for carrying out the data input/output in the common 1-bit unit will be described.
In a dynamic random access memory, a row address and a column address are generally supplied in a time-division multiplexing manner to address input terminals (which are A0-A9 in FIG. 1). The row and column addresses provided in a time-division multiplexing manner are respectively accepted at the falling edges of the row address strobe signal RAS and the column address strobe signal CAS under control of the RAS buffer 42 and the CAS buffer 46, so that the internal row address signals RA0-RA9 and the internal column address signals CA0-CA9 are generated. 9-bit internal row address signals RA0-RA8 out of 10-bit internal row address signals RA0-RA9 generated from the address buffer 14 are supplied to the row decoders 16a-16d. The row decoders 16a-16d decode these supply internal row address signals RA0-RA8 to select corresponding word lines. After stabilization of the word line selecting operation of the row decoders 16a-16d, a word line driving signal WL is generated by the word driver 18 to be transmitted onto a selected word line, whereby the selected word line is activated. As a result, information stored in memory cells MC connected to the selected word line is transmitted onto a bit line BL (or BL). The potential on the bit line BL (or BL) in a pair slightly changes according to the read-out information, while the potential on the other bit line BL (or BL) of the pair does not change, so that a potential difference occurs on the bit line pair BL, BL. The sense amplifiers 12a-12d are then activated in response to the sense amplifier activating signal from the sense amplifier control circuit 44, so that the potential difference on each of the bit line pairs is amplified. A unit column decoder of the column decoders 20a-20d is selected by the internal column address signals CA0-CA8, and its corresponding bit line pair BL, BL is connected to the data input/output lines I/O, I/O. According to a series of operations described above, in the data reading operation, the data of a 1-bit memory cell MC in the respective memory cell array blocks 10a-10d is transmitted onto the respective data input/output lines I/O1, I/O1-1/04, I/O4 and then to the respective preamplifiers 26a-26d. The preamplifiers 26a-26d further amplify received information. The most significant address bits RA9, CA9 of the internal address signals generated from the address buffer are supplied to the nibble decoder 29. The nibble decoder 29 selects only one of four outputs thereof in response to these most significant internal address signals RA9, CA9 to apply a selecting signal to the selecting gate 24. Accordingly, only one pair of the transistors Tr1-Tr8 included in the selecting gate 24 is turned on, so that the preamplifier output connected to this transistor pair is transmitted onto the internal data lines DB, DB. In a normal operation mode in 1-bit unit or in a rapid serial access mode such as a nibble mode, a test mode instructing signal TE is not generated, and the test control circuit 40 controls the reading gate 36 and connects the output buffer 38 to the internal data lines DB, DB. Therefore, the complementary data pair transmitted onto the internal data lines DB, DB is sent to the output buffer 38 and is output as the read-out data Dout from the output buffer 38 after translated into 1-bit data.
A write control signal W is logical high (the "H" level) in the above described data reading operation, whereby the writing gate 32 is non-conductive and the external input buffer 28 is not connected to the internal data lines DB, DB.
In the data writing operation, the external write control signal W is logical low (the "L" level) and the input buffer 28 is activated, and therefore the writing gate 32 is rendered conductive. Accordingly, a complementary input data pair Din, Din corresponding to write-in data Din generated by the input buffer 28 is transmitted onto the internal data lines DB, DB. The complementary data pair transmitted onto the internal data lines DB, DB is transmitted to a selected memory cell through the opposite path to the one in the above described data reading operation, and thus input data are written. The foregoing description is a summary of the data reading/writing operations in one memory cycle.
In a nibble operation mode as well as in a normal mode, a 1-bit memory cell (precisely one preamplifier) is first selected by the nibble decoder 22 responsive to the internal addresses RA9, CA9, and data is written in or read from the selected memory cell via the preamplifier selected by the nibble decoder 22. By sequentially toggling an external column address strobe signal CAS with a signal RAS kept at an active state, i.e., the "L" level, the nibble decoder 22 sequentially turns on the transfer gate transistor pairs in the selecting gate 24 in response to the toggle, thereby connecting the preamplifiers 26a-26d to the internal data lines DB, DB sequentially. Although the preamplifiers 26a-26d and the memory cell array blocks 10a-10d simultaneously transmit data, memory cells are sequentially accessed bit-by-bit from the memory cell array blocks 10a-10d so as to write or read the data of the memory cells when seen from the outside of the memory device,
In a functional testing mode operation in the semiconductor memory device, a test mode instructing signal TE is generated and all the transfer gate transistors Tr1-Tr8 in the selecting gate 24 are turned on by the nibble decoder 22 under the control of the test control circuit 40. Furthermore, the reading gate 36 connects the logic operation circuit 34 to the output buffer 38. In this functional testing mode, the complementary internal write-in data Din, Din received via the input buffer 28 are simultaneously transmitted to the memory cells selected in the four memory cell array blocks 10a-10d and are written therein, while in data reading, 4-bit memory cell data are sent to the logic operation circuit 34 via the preamplifiers 26a-26d. The logic operation circuit 34 receives the 4-bit data (precisely 8-bit data to be a complementary data pair) and, after performing a predetermined logic operation, outputs the data indicating a logic operation result thereof. The output buffer 38 receives the output of the logic operation circuit 34 output via the reading gate 36 to output the corresponding read-cut data Dout.
The foregoing description is a summary of the data reading/writing operations in one test cycle and hereinafter such operations will be described in further detail in conjunction with the configuration of a memory cell array portion.
FIG. 2 is diagram illustrating in more detail a major portion of one memory cell array block in the semiconductor memory device shown in FIG. 1. The configuration in FIG. 2 comprises memory cell array corresponding to 256K bit, sense amplifiers, and data input/output lines I/O, I/O. In FIG. 2, there are provided 512 word lines WL1-WL512, and 512 pairs of bit lines BL1, BLI-BL512, BL512 intersecting the 512 word lines WL1-WL512. A memory cell MC1 is provided at the intersection of a word lines WL1 and a bit line BL1, and a memory cell MC2 is provided at the intersection of a word line WL2 and a complementary bit line BL1. Similarly, a memory cell MC511 is provided at the intersection of a word line WL511 and the bit line BL1, while a memory cell MC512 is provided at the intersection of a word line WL512 and the complementary bit line BL1. That is, a folded bit line scheme is given in which one memory cell is provided at the intersection of one word line and either one bit line of a bit line pair, and a total of 512 memory cells are provided for 1 bit line pair. Each memory cell MC (which typically illustrates a memory cell) comprises a capacitor C0 for storing information in the form of a charge, and a transfer gate transistor Q0 which is turned on responsive to a word line potential to connect the capacitor C0 to its corresponding bit line BL (or BL). The transfer gate transistor Q0 is formed employing, for example, an n channel MOS transistor. The memory cell capacitor C0 is of, for example, a MOS (metal-insulation film-semiconductor) structure. One electrode of the memory cell capacitor C0 is connected to a power supply which outputs a predetermined constant voltage Vcp (for example, a 1/2 value of an operation supply voltage Vcc) developed on a semiconductor chip where the semiconductor memory device is provided.
A sense amplifier 2 is provided for each bit line pair BL, BL to sense and amplify a potential difference on the bit line pair. The sense amplifier 2 comprises a p MOS sense amplifier portion of a flip-flop type configuration comprising p channel MOS transistors Q3, Q4, and a nMOS sense amplifier portion of a flip-flop type comprising n channel MOS transistors Q1, Q2. A node N1 of the nMOS sense amplifier portion is connected to a signal line SN. A node N2 of the pMOS sense amplifier portion is connected to a signal line SP. The transistors Q1, Q2 have their gates and drains cross-coupled to each other and their sources connected to the signal line SN. Similarly, the transistors Q3, Q4 have their gates and drains cross-coupled to each other and their sources connected to the signal line SP.
A sense amplifier activating circuit 6 is provided for activating the sense amplifiers 2. The sense amplifier activating circuit 6 comprises an n channel MOS transistor Q10 which is turned on responsive to a sense amplifier activating signal S0 to connect the signal line SN to the ground potential level, and a p channel MOS transistor Q11 which is turned on responsive to a sense amplifier activating signal S0 to connect the signal line SP to the operation supply potential Vcc level. Therefore, in activation of the sense amplifiers 2, the nMOS sense amplifier portion discharges the potential on a lower potential bit line of a corresponding bit line pair to the ground potential, while the pMOS sense amplifier portion charges the potential on a higher potential bit line of a corresponding bit line pair to the operation supply potential Vcc level.
An equalizing/holding circuit 4 is provided for maintaining the potential of each bit line pair at a prescribed potential V.sub.BL in a standby period. The equalizing/holding circuit 4 comprises an n channel MOS transistor Q8 which is turned on responsive to an equalizing signal EQ to connect the bit line BLI to a signal line L.sub.BL, an n channel MOS transistor Q9 which is turned on responsive to the equalizing signal EQ to connect the complementary bit line BL1 to the signal line L.sub.BL, and an n channel MOS transistor Q7 which is turned on responsive to the equalizing signal EQ to inter connect the bit lines BL1, BL1. A holding voltage V.sub.BL is developed on the semiconductor chip where the semiconductor memory device is provided, in order to maintain the equalizing voltage level on each bit line (for example Vcc/2) when a row address strobe signal RAS externally provided is in the "H" level (i.e. the standby state).
An I/O gate 3 is provided for connecting a corresponding bit line pair to the data input/output lines I/O, I/O responsive to an external column address. The I/O gate 3 comprises an n channel MOS transistor Q5 which is turned on responsive to a column decoder output Y (column selecting signals Y1-Y512 are typically illustrated) to connect the bit line BL1 to the data input/output line I/O, and an n channel MOS transistor Q6 which is turned on responsive to the column selecting signal Y to connect the complementary bit line BL1 to the complementary data input/output line I/O.
A block 5 shown by a chain dotted line in FIG. 2 illustrates a 512-bit cell array including memory cells MC connected to one bit line pair, a sense amplifier 2, an equalizing/holding circuit 4 and an I/O gate 3. In the 256K bit memory cell array, 512 blocks 5 are arranged in parallel, and 512 unit column decoders are arranged corresponding to the 512 blocks 5. 256K bits now represent 262, 144 bits. Next, a one-cycle operation in the memory cell array block shown in FIG. 2 will be described with reference to a timing chart thereof in FIG. 3.
An equalizing signal EQ is almost synchronized with the row address strobe signal RAS externally provided and is at the "H" level before the time t1. Such state corresponds to the state that the row address strobe signal RAS is in the "H" level, i.e. the standby state of the semiconductor memory device. In this state, all the transistors Q7-Q9 in the equalizing/holding circuit 4 are on, and the potentials of the bit line pair BL, BL are equally Vcc/2. This precharging (or equalizing) potential is basically achieved by the fact that in the preceding operation cycle, one of the bit line BL and complementary bit line BL is at the operational supply potential Vcc while the other bit line is at the ground potential, and the equalizing transistor Q7 is rendered conductive at the end of the cycle. Therefore, the potential Vcc/2 need not be supplied from a supply potential VBL for holding. However, if the standby state lasts long, the holding potential V.sub.BL is supplied to each bit line BL, BL via the transistors Q8, Q9 in order to prevent the fluctuation of the equalizing/holding potential due to some noise. That is, the potential V.sub.BL is the supply potential for maintaining the bit line potential at a constant value.
First of all, a reading operation will be described. When the row address strobe signal RAS goes to the "L" level and the equalizing signal EQ goes to the "L" level as well, near the time t1, the transistors Q7-Q9 in the equalizing/holding circuit 4 are turned off, and bit line pairs BLi, BLi (i=1-512) are made to be in an electrically floating state. At this time, an external address is accepted into the memory device at the falling edge of the row address strobe signal RAS and is supplied to the row decoders as described above. As a result, one unit decoder out of the row decoders is selected.
When the word line driving signal WL is activated to rise to the "H" level at the time t2, one of the 512 word lines WL1-WL512, connected to the selected unit row decoder is selected, so that the potential thereof attains the "H" level. As shown in FIG. 2, there is provided a configuration in which one memory cell MC is selected for one word line in one block 5, and 512 memory cells for 512 bit line pairs are connected to this selected word line. Therefore, 512 memory cells are selected according to the selection of one word line. As a result, a charge stored in each of the selected memory cells is transmitted onto the bit line BL or BL. Since the ratio of a capacitance value C0' of the memory cell capacitor C0 to a capacitance value C.sub.BL of a bit line is normally and approximately 1:10, a change in the potential on the bit line by the read-out memory cell data is small and approximately 1/10 of the operational supply potential Vcc. If the selected memory cell stores the "H" level and is connected to the bit line BL1, the potential of the bit line BL1 slight by rises as shown by the solid line in an operation waveform diagram of FIG. 3. On the other hand, the potential of the complementary bit line BL remains at V.sub.cc/2 because a selected memory cell does not exist thereon.
When the sense amplifier activating signal S0 goes to the "H" level while the sense amplifier activating signal S0 goes to the "L" level at the time t3, the common source line (signal line) SN goes to the "L" level while the signal line SP attains the "H" level, so that the n MOS sense amplifier comprising the transistors Q1, Q2 and the pMOS sense amplifier comprising the transistors Q3, Q4 are activated so as to amplify the potential of the bit line BL1 to the "H" level and the potential of the complementary bit line BL1 to the "L" level. At this time, the potentials of the 512 bit line pairs are respectively changed to the "H" level or the "L" level by 512 sets of the sense amplifiers depending on information of the respective 512 memory cells selected.
When an internal column address is supplied to column decoders, and one unit column decoder included in the column decoders is selected, and therefore the output Yi thereof (Y1 in FIG. 3) attains the "H" level at the time t4, one of the 512 bit line pairs (BL1, BL1 in FIG. 3) is connected to the data input/output lines I/O, I/O via an I/O gate 3. As a result, the potential levels of the data input/output lines I/O, I/O already maintained at an electrically floating state, respectively change to the "H" level and the "L" level according to the levels of the bit lines connected thereto. After that, as mentioned above, the read-out data are further amplified in a preamplifier connected to the data input/output lines I/O, I/O, and they are supplied to the output buffer to be output as the output data Dout of the "H" level via this output buffer.
When the potential of the word line selected goes to the "L" level at the time t5 (FIG. 3 shows the state in which the word line WL1 is selected), the selected memory cells and the bit line BL (or BL) are electrically separated.
When the sense amplifier activating signals S0, S0 respectively goes to the "L" level and the "H" level, and the equalizing signal EQ attains the "H" level at the time t6, the bit line pair BL, BL are respectively equalized, so that the potentials thereon attains the level of Vcc/2 to be the standby state for the subsequent cycle. Accordingly, one memory cycle (operation cycle) is completed.
The potential level on the bit line BL (or BL) amplified during the time t3 to t5 is transmitted to the selected memory cells, so that this potential level is re-written into the selected memory cells. If the selected memory cell stores the "L" level, changes of signals shown by the dashed line in FIG. 3 are provided for the bit lines, and the read-out data from the data output buffer goes to the "L" level.
Next in the writing operation, if the level of the data input/output lines I/O, I/O is previously set to the "H" level or the "L" level not to the floating state, according to the value of the write-in data Din, the data input/output lines I/O, I/O and the selected one bit line pair are connected to each other at the time t4, so that the potential on the bit line pair selected attains the potential level corresponding to the write-in data, and this potential level is also written in the selected memory cell.
Note that the bit line BL is connected to the data input/output line I/O and the complementary bit line BL to the complementary data input/output line I/O in the above mentioned configuration. Therefore, for the memory cell connected to the complementary bit line BL paired with the bit line BL (for example, the memory cell connected to the word line WL2), an opposite value to the write-in data Din (for example, the "L" level as opposed to the "H" level) is written, and further even in data reading as for this memory cell, an opposite data value to the potential level written in this memory cell is output as the read-out data Dout from the output buffer. In this case, the data opposite in value to the external write-in data is written in the memory cell and the data opposite in value to that stored is read out as a read-out data in data reading. Thus, if seen from the outside of the semiconductor device, it means that the write-in data is read out as it is, and therefore no problem arises therein.
The central feature of the present invention is that at least one less than all memory cells selected simultaneously is connected to the data input/output buses I/O, I/O in a different manner from that of the remaining cells.
Furthermore, in a common semiconductor memory device, each of the memory cell array blocks is of the same configuration, so that only the memory cells connected to the bit line BL or the memory cells connected to the complementary bit line BL are selected simultaneously from each of the array blocks.
Next, the operation of the semiconductor memory device in a test mode will be described with reference to FIG. 1. In this case, the test mode instructing signal TE attains the "H" level to be applied to the test control circuit 40. The test mode control circuit 40 controls the nibble decoder 22 and makes all the outputs of the nibble decoder 22 be at the "H" level simultaneously, regardless of the values of the internal row address signal RAQ and the internal column address signal CA9. As a result, the transistors Tr1-Tr8 in the selecting gate 24 are all rendered conductive. In data writing, the data transmitted to the selecting gate 24 are all simultaneously transmitted to the respective memory cells of a total of 4 bits selected in the memory cell array blocks 10a-10d, respectively, and therefore the same data are written in the memory cells of 4 bits as well as in the previously described operation. Accordingly, the required time for data writing is reduced to 1/4 that of the scheme in which the data are written into the memory cells in 1-bit unit.
In data reading, the test control circuit 40 makes the reading gate 36 connect the output of the logic operation circuit 34 to the output buffer 38 in response to the signal TE. The 4-bit data read out in the same way as in the previously described reading operation are transmitted to the preamplifiers 26a-26d simultaneously. The 4-bit memory cell information is then transmitted to the logic operation circuit 34 to undergo logic operation process, and then sent to the output buffer 38 via the reading gate 36. The output buffer 38 amplifies the output of the logic operation circuit 34 and outputs the read-out data Dout corresponding to the result of this logic operation processing. Accordingly, the required time for data reading is reduced to 1/4 the required time for the scheme for accessing the memory cells in 1 bit unit to carry out functional testing. As mentioned heretofore, the test time in this test mode can be simply reduced to 1/4 the time in the conventional 1 bit unit scheme.
In the above mentioned prior art, a circuit configuration which is shown simplified in FIG. 4A and gives truth values shown in FIG. 4B, is employed as this logic operation circuit 34. Referring to FIG. 4A, the logic operation circuit 34 comprises an AND gate AN1 for receiving 4-bit memory cell data M0-M3 and an AND gate AN2 for receiving the inverted data of the 4-bit memory cell data M0-M3. The output buffer 38 comprises an n channel MOS transistor TR1 connected to an operational supply potential Vcc, and an n channel MOS transistor TR2 connected to a ground potential. The output of the AND gate AN1 is supplied to the gate of the transistor TR1, while the output of the AND gate AN2 is supplied to the gate of the transistor TR2. Read-out data Dout are output from the connecting point of the transistors Tr1 and Tr2. In the reconfiguration of FIG. 4A, the read-out data M0-M3 correspond to the data transmitted via the data input/output lines I/O1-I/O4, while the data M0-M3 correspond to the data transmitted via the input/output data lines I/O1-I/O4. Further, in the truth table shown in FIG. 4B, the numeral "0" represents the case that a selected memory cell outputs the "L" level, while the numeral "1" represents the case that the selected memory cell outputs the "H" level. As clearly seen from the truth table shown in FIG. 4B, when the logic operation circuit shown in FIG. 4A is employed, if all the selected 4-bit memory cells output "0", the output data Dout are "0", while if all the read-out data are "1", the read-out data Dout are "1". Further, in case of the 4-bit read-out data with at least one bit different from the others, the output data Dout are at a high impedance (Hi-Z) state. This scheme is usually called a 3-value output scheme. As described above, since the same data are written in the 4-bit memory cells simultaneously, when the memory cells function normally, all the data outputted from the selected 4-bit memory cells are the same. Therefore, in this 3-value output scheme, the output data is not provided (the high impedance state) except when the memory cells function normally, so that detection of defects by a detecting device is easily carried out particularly upon unit testing (testing of a single device). In addition, even if all the selected 4-bit memory cells are defective, the data value thereof are output as they are, so that the output data can be easily seen and all the defective states can be detected by the detecting device.
Meanwhile, a 2-value output scheme which does not include this high impedance state is considered and proposed in the article entitled "A 90ns 4Mb DRAM in a 300mil DIP" by Mashiko et al in the IEEE; Digest of Technical Papers, 1987, pp. 12-13. This 2-value output scheme, of which the circuit configuration and truth table are shown in FIGS. 5A and 5B, respectively, is the scheme in which if all the 4-bit memory cells output the same data, "1" is output as the output data Dout, if even 1 bit of the memory cells is defective and its output data is different from those of others, "0" is output as the output data Dout. This scheme is about to be standardized in a 4 megabit DRAM.
FIG. 5A is a diagram illustrating one example of the simplified configuration of the logic operation circuit in this 2-value output scheme. FIG. 5B is a truth table showing its truth values. Referring to FIG. 5A, the logic operation circuit 34 of the 2-value output scheme 34 comprises an AND gate AN3 for receiving the outputs of 4 bit memory cell data M0-M3, an AND gate AN4 for receiving the inverted data of the 4-bit memory cell data M0-M3, an OR gate O1 for receiving the outputs of the AND gates AN3, AN4, and an inverter Il for inverting the output of the OR gate O1. The output of the OR gate O1 is supplied to the gate of a transistor TR1 included in the output buffer 38, while the output of the inverter Il is supplied to the gate of a transistor TR2 included in the output buffer 38.
As described above, the time required for the function test of the semiconductor memory device is reduced by simultaneously accessing the memory cells of a plurality of bits and carrying the functional testing of the memory cells in the unit of the plurality of bits; however, the following problems arise in the semiconductor memory device having a conventional test mode of 2-value output scheme. Assuming that all the 4-bit memory cells selected simultaneously are defective, for example, all the read-out data from the 4-bit memory cells are "0" although "1" is written in all the 4-bit memory cells, the output data Dout are "1" as shown in FIG. 5B, so that the semiconductor memory device is determined as good (pass).
When such defects in the memory cells are, for example, fixed defects such as a pattern defects which occur in manufacturing of the semiconductor memory device, the memory device having such defects can be removed by testing all the bits in advance according to a test in the normal mode (access in a 1-bit unit). As a matter of course, a benefit of reduction in the test time is lost in this case.
However, if the foregoing problem arises in a test for checking an operating margin such as a timing margin, a voltage margin etc., the functional testing cannot be carried out in the test mode. The timing margin is a margin indicating the tolerance of a deviation in the operation timing of a control signal in the device in which the semiconductor memory device can operate correctly. The voltage margin is, for example, a margin indicating an allowable fluctuation range of an operation supply voltage within which the semiconductor memory device normally operates. As an example of such function testing, a refresh margin test is reviewed.
As described above, in a memory cell of the DRAM, information is stored in a memory cell capacitor (MOS capacitor) in the binary form of "1" (corresponding to the "H" level) or "0" (corresponding to the "L" level). Particularly, the state in which "1" is stored and a written potential is the "H" level, which, by convention, corresponds to the depleted state where no electrons exist in a memory capacitor portion, is thermally nonequilibriated. In contrast, the "L" level is stable. Therefore, if this memory cell is maintained in a non-access state (a standby state) for a long period of time, electrons are collected in the depleted capacitor storing "H" level little by little such as by a junction leak (a leak through a junction portion between a semiconductor substrate and an impurity region providing for the capacitor portion), and information thereof changes to the "0" state. Accordingly, it is necessary to read the information of each memory cell to be rewritten in a predetermined period of time. This operation is usually called "refresh". The refresh margin test is the one for checking if a memory cell keeps correct information, e.g. how long a period from one refresh to the next refresh would be. In this refresh margin test, a defect occurs in the memory cell only when "1" is stored therein, so that no defect is seen in the memory cell storing "0" (the state in which electrons fill the memory capacitor). That is, only an error consisting of a "1" .fwdarw."0" transition of the memory cell occurs in this refresh margin test. Problems which may occur in the refresh margin test will be described hereinafter in detail. For example, it is assumed that such a test is carried out that "1" is written in the memory cells of all the bits in the semiconductor memory device and is maintained in the standby state for a certain period of time (which is called a data holding time), and then is read out. If the data holding time is short, the data of each memory cell are correctly held, whereas if the data holding time is extremely long, there occurs an inversion of the memory cell data, resulting in a defect in the memory cell. Namely, the error consisting of "1".fwdarw."0" transition of the memory cell arises. However, when this test is carried out in the test mode of the 2-value output scheme, even if all the memory cells selected caused the error "1".fwdarw."0", all the outputs of the selected 4-bit memory cells coincide with each other. Accordingly, the output data Dout are "1" according to the truth table shown in FIG. 5B, so that the semiconductor memory device is determined as good.
Furthermore, problems which may occur in the voltage margin test will now be described with reference to FIGS. 6A and 6B. For example, a case is considered in which "1" is written in all the memory cells of the semiconductor memory device so as to carry out a test to read this write-in data with the operation supply voltage varied. In this case, it is necessary to check if the semiconductor memory device normally operates in the operation supply potential in a range of 4.5-5.5 V as guaranteed by specifications. It is assumed that there is a semiconductor memory device causing malfunctions at the operation supply potential below 4.75 V in the test in the normal mode (1-bit unit access) as shown in FIG. 6A. That is, it is simply assumed that the operating margin for "1" is small at the operation supply voltage below 4.75 V, and even if the data "1" are written in the memory cell, "0" is output from the memory cell. In a case that this semiconductor memory device is tested in the test mode of the 2-value output scheme, when the operation supply potential is greater than 4.75 V, each memory cell outputs the data of "1" if the data of "1" is written, so that the semiconductor memory device is determined as good as shown in FIG. 6B, and therefore no problem arises. However, when "1" is written in the memory cell with the operation supply potential less than 4.5 V, all the memory cells selected output "0", so that the output data Dout is "1" according to the truth table shown in FIG. 5B, and therefore this semiconductor device is determined as good. In FIG. 6B, a transition region is illustrated in an enlarged manner, which exists between one case in which all the memory cells are defective and the other case in which all the memory cells "pass" (namely, a region where some memory cells operate correctly, while the others are defective). However, this transition region does not exist in such an ideal state that all the memory cells are formed to be exactly the same.
In the actual checking of the semiconductor memory device when marketed, in order to reduce the testing time, the functional testing is not carried out many times with many variations in the operation supply voltage, typically, at least, it is carried out by using three or four points of the operation supply voltage, for example, 4.3 V or so. Therefore, there arises a problem that in this checking of the semiconductor memory device, the semiconductor memory device is determined as no good in the functional testing in the normal mode as shown in FIG. 6A, is determined as good as shown in FIG. 6B.